View ISL95813_6467476.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 single phase core controller for vr12.6 ISL95813 the ISL95813 single-phase controller provides a fully compliant vr12.6 power supply solution for intel? microprocessors. it provides a tightly regulated outp ut voltage that is programmed through a high speed serial bu s interface with the cpu. this interface also allows the cpu to acquire real-time information from the voltage regulator (vr), which includes load current and vr temperature. based on intersil's robust ripple regulator (r3?) technology, the pwm modulator provides faster transient response and settling time when compared ag ainst traditional modulation schemes. its variable frequency topology also allows for natural period stretching discontinuous conduction mode (d cm) for increased efficiency and power savings in light load situations. the ISL95813 has several other key features that include: dcr current sensing with single ntc thermal compensation; discrete resistor current sensing; differential remote voltage feedback; and user-programmable boot voltage, i max , t max , voltage transition slew rate, and switching frequency. features ? full vr12.6 specification compliance ? wide input voltage range: 4.6v to 25v ? r3? control architecture delivers excellent transient response and power state mode transitions ? current monitor (imon) with temperature compensation ? vrhot# indicator for cpu protection ? digitally selectable switching frequency: - 425khz, 550khz, 700khz with eco and pro options ? enhanced light-load efficiency discontinuous conduction mode operation ? ultra-small 20 lead 3mmx4mm qfn package ? enable and power-good monitor applications ? notebook computers ? tablets, ultrabooks?, and aio related literature ? an1846 designer?s guide to the ISL95813 evaluation board e-pad (gnd) vrhot# ntc vr_on imon pgood comp fb rtn isumn isump lg phase ug boot vcc pgrm2 sclk alert# sda prgm1 lout cout vr12.6 cpu vtt 1 2 3 4 6 5 16 15 14 13 11 12 78910 20 19 18 17 6800pf 0.22f 1f 0.15h 0.056f bsc052n03ls ISL95813 20 ld 3x4 qfn 14x22f ceramic 2200pf vin {4.6v to 25v} 10k (ntc) 205k 113k 124k 1.82k 549 3.65k 2.61k 11k 3.83k 5.9k 27.4k 470k (ntc) 499 82pf bsc011n03ls figure 1. typical 40amax, 12.6, application diagram caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved r3 technologies and intersil (and design) are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. may 15, 2013 fn8449.0 http://www..net/ datasheet pdf - http://www..net/
ISL95813 2 fn8449.0 may 15, 2013 pin configuration ISL95813 (20 ld 3x4 qfn) top view ordering information part number (notes 1, 2) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL95813hrz 813h -10 to +100 20 ld 3x4 qfn l20.3x4 ISL95813irz 813i -40 to +100 20 ld 3x4 qfn l20.3x4 ISL95813ev1z evaluation board notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL95813 . for more information on msl, please see tech brief tb363 . sclk alert# sda prgm1 fb rtn isumn isump vr_on pgood imon vrhot# ntc comp lg phase ug boot vcc prgm2 1 2 3 4 5 6 16 15 14 13 12 11 20 19 18 17 78910 gnd pin descriptions pin name function 1 vr_on digital input enable input for cont roller. connect to ground to disable the part. connect to vcc to initiate soft-start and regulation. 2 pgood digital output power-good open-drain output indicating wh en vr is in regulation with no faults detected. pull up externally with a 680 resistor to vccp or 1.9k to 3.3v. 3imonanalog output: [small-signal] vr output current monitor. imon pin sources a current proportional to the regulator output current. a resistor connected from this pin to ground will set a voltage that is proportional to the load current. this voltage is sampled with an internal adc to produce a digital imon signal that can be read through the serial communications bus. 4 vrhot# digital output open drain thermal overload output indi cator. can be considered part of communication bus with cpu. 5ntcanalog input: [small-signal] thermistor input to vr_hot# circuit. used to monitor vr temperature. 6 comp analog output: [small-signal] output of the gm error-amplifier for loop contro l. connect to ground through the compensation network. http://www..net/ datasheet pdf - http://www..net/
ISL95813 3 fn8449.0 may 15, 2013 7fbanalog input: [small-signal] output voltage feedback sensing input for regulation. connect via resistor to vcc sense on cpu. 8rtnanalog input: [small-signal] ground return for differential remote output voltage sensing.connect via resistor to vcc sense on cpu. 9isumnanalog input: [small-signal] vr loadline, droop, and dcr sensing input. 10 isump analog input: [small-signal] vr loadline, droop, and dcr sensing input. 11 prgm2 analog input: [small-signal] adc input to program switching frequency and bo ot voltage using a resistor to ground. see ?program 2 pin? on page 13 for all programming options. 12 vcc analog input: [small-signal] 5v ic bias supply input. bypass to ground with a high-quality 0.1f ceramic capacitor. 13 boot analog input: [power] floating high-side gate drive voltage supply. conne ct to phase with a 0.1f to 0.22f high-quality ceramic capacitor. 14 ug analog output: [power] upper mosfet gate drive. connect with a wide tr ace to the gate of the upper switching mosfet. 15 phase analog i/o: [power] switching node and upper mosfet gate drive return path. connect with a wide trace to the source of the upper switching mosfet, the drain of the lower switching mosfet, and the output inductor. 16 lg analog output: [power] lower mosfet gate drive. connect with a wide trace to the gate of the lower switching mosfet. 17 prgm1 analog input: [small-signal] adc input to program i ccmax and fsel bit using a resistor to ground. see ?program 1 pin? on page 13 for all programming options. 18 sda digital i/o data input/output for cpu serial interface. 19 alert# digital output alert signal for cpu serial interface. 20 sclk digital input clock input for cpu serial interface. e-pad gnd analog input: [power] ground reference for ic as well as gate drive power ground return path. connect to system ground plane with multiple vias. pin descriptions (continued) pin name function http://www..net/ datasheet pdf - http://www..net/
ISL95813 4 fn8449.0 may 15, 2013 absolute maximum rating s thermal information supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . . . phase-0.3v (dc) to boot . . . . . . . . . . . . . . . . . . . . . p hase-5v (<20ns pulse width, 10j) to boot lgate voltage . . . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) open drain outputs, pgood, vr_hot#, alert#. . . . . . . . . . -0.3v to +7v thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 4, 5) . . . . . . . . 44 6 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6v to 25v ambient temperature hrz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c irz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c junction temperature hrz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c irz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vdd = 5v, t a = -10c to +100c or -40c to +100c, f sw = 700khz, unless otherwise noted. boldface limits apply over the operating temp erature range for high temp commercial at -10c to +100c or industrial temp at -4 0c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd vr_on = 1v 3.5 5 ma vr_on = 0v 1 a ps4 state 90 150 a power-on-reset thresholds vdd power-on-reset threshold vddpor r v dd rising 4.35 4.5 v vddpor f v dd falling 4.00 4.15 v system and references system accuracy hrz %error (v out) vid = 1.50v to 2.30v -0.5 +0.5 % vid = 1.00v to 1.49v -8 +8 mv vid = 0.50v to 0.99v -10 +10 mv irz %error (v out ) vid = 1.50v to 2.30v -1 +1 % vid = 1.00v to 1.49v -15 +15 mv vid = 0.50v to 0.99v -20 +20 mv internal v boot hrtz (set by r_prog2) 1.683 1.7 1.717 v irtz (set by r_prog2) 1.675 1.7 1.725 v maximum output voltage v out(max) vid = [11111111] 2.3 v minimum output voltage v out(min) vid = [00000001] 0.5 v http://www..net/ datasheet pdf - http://www..net/
ISL95813 5 fn8449.0 may 15, 2013 channel frequency 425khz configuration f sw_425k set by r_prog1 395 425 455 khz 550khz configuration f sw_550k 510 550 590 khz 700khz configuration f sw_700k 650 700 750 khz 1000khz configuration f sw_1000k set by r_prog1 (pro ps2/ps3 only) 915 985 1055 khz amplifiers current-sense amplifier input offset i fb = 0a, hrz -0.2 +0.2 mv i fb = 0a, irz -0.3 +0.3 mv error amp dc gain (note 7) a v0 90 db error amp gain-bandwidth product (note 7) gbw c l = 20pf 18 mhz power-good and protection monitors pgood low voltage v ol i pgood = 4ma 0.15 0.4 v pgood leakage current i oh pgood = 3.3v 1 a pgood delay tpgd v boot = 1.7v 1.2 ms alert# low voltage (note 6) 7 12 vr_hot# low voltage (note 6) 7 12 alert# leakage current 1 a vr_hot# leakage current 1 a gate driver ugate pull-up resistance (note 7) r ugpu 200ma source current 1.0 1.5 ugate source current (note 7) i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance (note 7) r ugpd 250ma sink current 1.0 1.5 ugate sink current (note 7) i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance (note 7) r lgpu 250ma source current 1.0 1.5 lgate source current (note 7) i lgsrc lgate - gnd= 2.5v 2.0 a lgate sink resistance (note 7) r lgpd 250ma sink current 0.5 0.9 lgate sink current (note 7) i lgsnk lgate - gnd = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 17 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 29 ns bootstrap diode on-resistance r f 22 ? reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h isumn rising above setpoint for >1s 240 300 360 mv overcurrent threshold 56 60 64 a logic thresholds vr_on input low v il 0.3 v vr_on input high v ih hrz 0.7 v v ih irz 0.75 v thermal monitor ntc source current ntc = 1.3v 58 60 62 a vr_hot# trip voltage falling 0.881 0.893 0.905 v vr_hot# reset voltage rising 0.924 0.936 0.948 v electrical specifications operating conditions: vdd = 5v, t a = -10c to +100c or -40c to +100c, f sw = 700khz, unless otherwise noted. boldface limits apply over the operating temp erature range for high temp commercial at -10c to +100c or industrial temp at -4 0c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units http://www..net/ datasheet pdf - http://www..net/
ISL95813 6 fn8449.0 may 15, 2013 therm_alert trip voltage falling 0.92 0.932 0.944 v therm_alert reset voltage rising 0.962 0.974 0.986 v current monitor imon output current i imon isumn pin current = 40a 9.7 10 10.3 a isumn pin current = 20a 4.8 5 5.2 a isumn pin current = 4a 0.875 1 1.125 a i ccmax alert trip voltage v imonmax rising 1.185 1.2 1.215 v i ccmax alert reset voltage falling 1.122 1.14 1.152 v inputs vr_on leakage current i vr_on vr_on = 0v -1 01a vr_on = 1v 3 5 a sclk, sda leakage vr_on = 0v, sclk & sda = 0v & 1v -1 1 a vr_on = 1v, sclk & sda = 1v -5 1 a vr_on = 1v, sclk & sda = 0v, sclk -42 a vr_on = 1v, sclk & sda = 0v, sda -21 a slew rate (for vid change) fast slew rate set by r_prog2 12 mv/s slow slew rate default setting fast slew divided by 4 3 mv/s notes: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 7. limits established by characteriza tion and are not production tested. electrical specifications operating conditions: vdd = 5v, t a = -10c to +100c or -40c to +100c, f sw = 700khz, unless otherwise noted. boldface limits apply over the operating temp erature range for high temp commercial at -10c to +100c or industrial temp at -4 0c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units http://www..net/ datasheet pdf - http://www..net/
ISL95813 7 fn8449.0 may 15, 2013 gate driver timing diagram pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr typical performance waveforms (v in = 19v, 700khz, pro) figure 2. ps0, 1-35a load release figure 3. ps0, 1-35a high rep load transient figure 4. ps0, 1-35a load insertion figure 5. ps3 to ps0, 1-35a transient figure 6. ps0, set vid fast from 1.6v to 1.8v figure 7. ps0, set vid fast from 1.8v to 1.6v vid = 1.8v vid = 1.8v vid = 1.8v vid = 1.8v 53mv/s 10a load 53mv/s 10a load http://www..net/ datasheet pdf - http://www..net/
ISL95813 8 fn8449.0 may 15, 2013 figure 8. ps0, set vid fast from 1.6v to 1.8v figure 9. ps0, set vid fast from 1.8v to 1.6v figure 10. ps4 exit to 1.6v, io = 1a, slewrate = 53mv/s typical performance waveforms (v in = 19v, 700khz, pro) 13.5mv/s 10a load 13.5mv/s 10a load rtn e/a fb idroop current sense isump isumn comp vcc ov fault pgood _ + _ + + + driver driver lgate phase ugate boot oc fault digital interface sda alert# sclk dac temp monitor ntc vr_hot# t_monitor imax vboot droop prog vr_on mode d/a a/d idroop r3 modulator gnd prgm1 prgm2 vin imon figure 11. block diagram http://www..net/ datasheet pdf - http://www..net/
ISL95813 9 fn8449.0 may 15, 2013 theory of operation r 3? modulator the r 3? modulator is intersil?s proprietary synthetic current- mode hysteretic controller and is a blend of fixed frequency pwm and variable frequency hysteretic control technology. this modulator topology offers high noise immunity and a rapid transient response to dynamic load scenarios. under static conditions the desired switching frequency is maintained within the entire specified range of inpu t voltages, output voltages, and load currents. during load transients the controller will increase or decrease the pwm pulses and switching frequency to maintain output voltage regulation. figure 12 illustrates this effect during a load insertion. as the window voltage starts to climb from a load step the time between pwm pulses decreases as f sw increases to keep the output within regulation. diode emulation and period stretching the ISL95813 can operate in di ode emulation (de) mode to improve light load efficiency. in de mode, the low-side mosfet conducts only when the current is flowing from source to drain and does not allow reverse current, emulating a diode like a standard buck regulator. as figure 13 shows, when lgate is on, the low-side mosfet conducts, creating negati ve voltage on the phase node due to the voltage drop across the on-resistance. the controller monitors the current through monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing direction. if the load current reaches the critical conduction point the inductor current will reach and stay at zero before the next phase node pulse and the regulator is in discontinuous conduction mode (dcm). should the load current rise above the critical conduction point, the inductor current will not cross 0a in a switching cycle, and the regula tor is in ccm although the controller is in de mode.equation 1 below gives the formula for critical conduction, where i critical is the load current for critical conduction and i l is the ripple on the inductor current. figure 14 shows the operation prin ciple in diode emulation mode at light load. the load gets increm entally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the peak inductor current the same in the three ca ses. the controller clamps the synthetic current de mode to make it mimic the inductor current. it takes the synthesized current longer to hit the lower window voltage, naturally stretching th e switching period. the inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. by reducing the switching frequency in de mode switching losses are decreased and light load efficiency is improved. eco and pro mode dcm the ISL95813 has the ability to set both eco and pro mode dcm options for 700khz switching app lications. in eco mode the time from upper gate on to lower gate off is set to 1 / 700khz or 1.43s. when pro mode is selected the ug on to lg off time is reduced to 1 / 1mhz or 1.0s. for applications where efficiency is important eco mode should be implemented as the longer switching times reduce the amount of switching loss in the fets. pro mode is ideal for applications that require lower dcm ripple as the shorter gate times reduce the amount of output ripple. because of the reduced ripple in pro mode the amount of output figure 12. modulator waveforms during load transient pwm synthetic current signal error amplifier window voltage v w (wrt v comp ) voltage v comp ugate phase il lgate vout vout figure 13. diode emulation i critical i l 2 ------- - = (eq. 1) i l i l i l synthetic current vw ccm/dcm boundary light dcm deep dcm vw vw synthetic current synthetic current figure 14. period stretching http://www..net/ datasheet pdf - http://www..net/
ISL95813 10 fn8449.0 may 15, 2013 capacitance can be reduced, saving both board space and bom costs. see ?program 1 resistor values? on page 13 for the eco/pro programming resistor options. start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins when vr_on exceeds the logic high threshold. figure 15 shows the typical start-up timing. the controller uses digita l soft-start to ramp-up dac to the voltage programmed by the setvid comman d. pgood is asserted high and alert# is asserted low at the end of the ramp up. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 1.1ms after v dd crosses the por threshold. voltage regulation and load line implementation after the start-up sequence, the controller regulates the output voltage to the value set by the vid information in table 1. the controller will control the no-load output voltage to an accuracy of 0.5% over the vid voltage range. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. current silicon maximum vid is set as 2.3v, and any vid command above 2.3v will be rejected. table 1. vid table vid hex v o (v) 7 6 5 4 3 2 1 0 vr12.6 0 0 0 0 0 0 0 0 0 0 0.00000 0 0 0 0 0 0 0 1 0 1 0.50000 0 0 000 0 1002 0.51000 0 0 0 0 0 0 1 1 0 3 0.52000 0 0 0 0 0 1 0 0 0 4 0.53000 0 0 0 0 0 1 0 1 0 5 0.54000 0 0 0 0 0 1 1 0 0 6 0.55000 0 0 0 0 0 1 1 1 0 7 0.56000 0 0 0 0 1 0 0 0 0 8 0.57000 0 0 0 0 1 0 0 1 0 9 0.58000 0 0 0 0 1 0 1 0 0 a 0.59000 0 0 0 0 1 0 1 1 0 b 0.60000 0 0 001 1 000c 0.61000 vdd vr_on dac 1.1ms dvid-slow v boot slew rate vid command voltage pgood alert# ?... figure 15. soft-start waveforms 0 0 0 0 1 1 0 1 0 d 0.62000 0 0 0 0 1 1 1 0 0 e 0.63000 0 0 0 0 1 1 1 1 0 f 0.64000 0 0 0 1 0 0 0 0 1 0 0.65000 0 0 0 1 0 0 0 1 1 1 0.66000 0 0 0 1 0 0 1 0 1 2 0.67000 0 0 0 1 0 0 1 1 1 3 0.68000 0 0 0 1 0 1 0 0 1 4 0.69000 0 0 0 1 0 1 0 1 1 5 0.70000 0001011016 0.71000 0 0 0 1 0 1 1 1 1 7 0.72000 0 0 0 1 1 0 0 0 1 8 0.73000 0 0 0 1 1 0 0 1 1 9 0.74000 0 0 0 1 1 0 1 0 1 a 0.75000 0 0 0 1 1 0 1 1 1 b 0.76000 000111001c 0.77000 0 0 0 1 1 1 0 1 1 d 0.78000 0 0 0 1 1 1 1 0 1 e 0.79000 0 0 0 1 1 1 1 1 1 f 0.80000 0010000020 0.81000 0 0 1 0 0 0 0 1 2 1 0.82000 0 0 1 0 0 0 1 0 2 2 0.83000 0010001123 0.84000 0 0 1 0 0 1 0 0 2 4 0.85000 0 0 1 0 0 1 0 1 2 5 0.86000 0010011026 0.87000 0 0 1 0 0 1 1 1 2 7 0.88000 0 0 1 0 1 0 0 0 2 8 0.89000 0 0 1 0 1 0 0 1 2 9 0.90000 001010102a 0.91000 0 0 1 0 1 0 1 1 2 b 0.92000 0 0 1 0 1 1 0 0 2 c 0.93000 0 0 1 0 1 1 0 1 2 d 0.94000 0 0 1 0 1 1 1 0 2 e 0.95000 0 0 1 0 1 1 1 1 2 f 0.96000 0 0 1 1 0 0 0 0 3 0 0.97000 0 0 1 1 0 0 0 1 3 1 0.98000 0 0 1 1 0 0 1 0 3 2 0.99000 0011001133 1.00000 table 1. vid table (continued) vid hex v o (v) 7 6543 2 10 vr12.6 http://www..net/ datasheet pdf - http://www..net/
ISL95813 11 fn8449.0 may 15, 2013 0 0 110 1 0034 1.01000 0 0 1 1 0 1 0 1 3 5 1.02000 0 0 1 1 0 1 1 0 3 6 1.03000 0 0 1 1 0 1 1 1 3 7 1.04000 0 0 1 1 1 0 0 0 3 8 1.05000 0 0 1 1 1 0 0 1 3 9 1.06000 0 0 1 1 1 0 1 0 3 a 1.07000 0 0 1 1 1 0 1 1 3 b 1.08000 0 0 1 1 1 1 0 0 3 c 1.09000 0 0 1 1 1 1 0 1 3 d 1.10000 0 0 111 1 103e 1.11000 0 0 1 1 1 1 1 1 3 f 1.12000 0 1 0 0 0 0 0 0 4 0 1.13000 0 1 0 0 0 0 0 1 4 1 1.14000 0 1 0 0 0 0 1 0 4 2 1.15000 0 1 0 0 0 0 1 1 4 3 1.16000 0 1 0 0 0 1 0 0 4 4 1.17000 0 1 0 0 0 1 0 1 4 5 1.18000 0 1 0 0 0 1 1 0 4 6 1.19000 0 1 0 0 0 1 1 1 4 7 1.20000 0 1 001 0 0048 1.21000 0 1 0 0 1 0 0 1 4 9 1.22000 0 1 0 0 1 0 1 0 4 a 1.23000 0 1 0 0 1 0 1 1 4 b 1.24000 0 1 0 0 1 1 0 0 4 c 1.25000 0 1 0 0 1 1 0 1 4 d 1.26000 0 1 001 1 104e 1.27000 0 1 0 0 1 1 1 1 4 f 1.28000 0 1 0 1 0 0 0 0 5 0 1.29000 0 1 0 1 0 0 0 1 5 1 1.30000 0 1 010 0 1052 1.31000 0 1 0 1 0 0 1 1 5 3 1.32000 0 1 0 1 0 1 0 0 5 4 1.33000 0 1 0 1 0 1 0 1 5 5 1.34000 0 1 0 1 0 1 1 0 5 6 1.35000 0 1 0 1 0 1 1 1 5 7 1.36000 0 1 0 1 1 0 0 0 5 8 1.37000 0 1 0 1 1 0 0 1 5 9 1.38000 0 1 0 1 1 0 1 0 5 a 1.39000 table 1. vid table (continued) vid hex v o (v) 7 6 5 4 3 2 1 0 vr12.6 010110115b 1.40000 010111005c 1.41000 010111015d 1.42000 010111105e 1.43000 010111115f 1.44000 0110000060 1.45000 0110000161 1.46000 0 1 1 0 0 0 1 0 6 2 1.47000 0110001163 1.48000 0110010064 1.49000 0110010165 1.50000 0110011066 1.51000 0110011167 1.52000 0110100068 1.53000 0 1 1 0 1 0 0 1 6 9 1.54000 011010106a 1.55000 011010116b 1.56000 0 1 1 0 1 1 0 0 6 c 1.57000 011011016d 1.58000 011011106e 1.59000 011011116f 1.60000 0111000070 1.61000 0111000171 1.62000 0111001072 1.63000 0111001173 1.64000 0111010074 1.65000 0111010175 1.66000 0111011076 1.67000 0111011177 1.68000 0111100078 1.69000 0111100179 1.70000 011110107a 1.71000 011110117b 1.72000 011111007c 1.73000 0 1 1 1 1 1 0 1 7 d 1.74000 011111107e 1.75000 011111117f 1.76000 1000000080 1.77000 1000000181 1.78000 table 1. vid table (continued) vid hex v o (v) 7 6543 2 10 vr12.6 http://www..net/ datasheet pdf - http://www..net/
ISL95813 12 fn8449.0 may 15, 2013 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the controller can sense the inductor current through the intrin sic dc resistance (dcr) of the inductors as shown in the typical applications diagram or through a current sense resistor in series with the inductor (figure 24). in both methods, the capacitor c n voltage represents the inductor total current. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitor and overcurrent protection. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. 1 0 0 0 0 0 1 0 8 2 1.79000 1 0 0 0 0 0 1 1 8 3 1.80000 1 0 000 1 0084 1.81000 1 0 0 0 0 1 0 1 8 5 1.82000 1 0 0 0 0 1 1 0 8 6 1.83000 1 0 0 0 0 1 1 1 8 7 1.84000 1 0 0 0 1 0 0 0 8 8 1.85000 1 0 0 0 1 0 0 1 8 9 1.86000 1 0 0 0 1 0 1 0 8 a 1.87000 1 0 0 0 1 0 1 1 8 b 1.88000 1 0 0 0 1 1 0 0 8 c 1.89000 1 0 0 0 1 1 0 1 8 d 1.90000 1 0 001 1 108e 1.91000 1 0 0 0 1 1 1 1 8 f 1.92000 1 0 0 1 0 0 0 0 9 0 1.93000 1 0 0 1 0 0 0 1 9 1 1.94000 1 0 0 1 0 0 1 0 9 2 1.95000 1 0 0 1 0 0 1 1 9 3 1.96000 1 0 0 1 0 1 0 0 9 4 1.97000 1 0 0 1 0 1 0 1 9 5 1.98000 1 0 0 1 0 1 1 0 9 6 1.99000 1 0 0 1 0 1 1 1 9 7 2.00000 1 0 011 0 0098 2.01000 1 0 0 1 1 0 0 1 9 9 2.02000 1 0 0 1 1 0 1 0 9 a 2.03000 1 0 0 1 1 0 1 1 9 b 2.04000 1 0 0 1 1 1 0 0 9 c 2.05000 1 0 0 1 1 1 0 1 9 d 2.06000 1 0 0 1 1 1 1 0 9 e 2.07000 1 0 0 1 1 1 1 1 9 f 2.08000 1 0 1 0 0 0 0 0 a 0 2.09000 1 0 1 0 0 0 0 1 a 1 2.10000 1 0 1 0 0 0 1 0 a 2 2.11000 1 0 1 0 0 0 1 1 a 3 2.12000 1 0 1 0 0 1 0 0 a 4 2.13000 1 0 1 0 0 1 0 1 a 5 2.14000 1 0 1 0 0 1 1 0 a 6 2.15000 1 0 1 0 0 1 1 1 a 7 2.16000 1 0 1 0 1 0 0 0 a 8 2.17000 table 1. vid table (continued) vid hex v o (v) 7 6 5 4 3 2 1 0 vr12.6 1 0 1 0 1 0 0 1 a 9 2.18000 1 0 1 0 1 0 1 0 a a 2.19000 1 0 1 0 1 0 1 1 a b 2.20000 1 0101 1 00ac 2.21000 1 0 1 0 1 1 0 1 a d 2.22000 1 0 1 0 1 1 1 0 a e 2.23000 1 0 1 0 1 1 1 1 a f 2.24000 1 0 1 1 0 0 0 0 b 0 2.25000 1 0 1 1 0 0 0 1 b 1 2.26000 1 0 1 1 0 0 1 0 b 2 2.27000 1 0 1 1 0 0 1 1 b 3 2.28000 1 0 1 1 0 1 0 0 b 4 2.29000 1 0 1 1 0 1 0 1 b 5 2.30000 table 1. vid table (continued) vid hex v o (v) 7 6543 2 10 vr12.6 figure 16. differential sensing and load line implementation x 1 e/a dac vid rdroop idroop vdac vdroop fb comp vcc sense vss sense vids rtn gnd internal to ic catch resistor catch resistor vr local vo i droop v cn r i ---------- - = (eq. 2) http://www..net/ datasheet pdf - http://www..net/
ISL95813 13 fn8449.0 may 15, 2013 i droop flows through resistor r droop and creates a voltage drop as shown in equation 3. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential voltage sensing figure 16 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and add it to the dac output. the error amplifier regulates the invertin g and the non-inverting input voltages to be equal as shown in equation 4: rewriting equation 4 and substitution of equation 3 gives equation 5 is the exact equa tion required for load line implementation. the vcc sense and vss sense signals come from the processor die. the feedback will be open circuit in the absence of the processor. as figure 16 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without a processor installed. ccm switching frequency the prog2 pin configures the ccm switching frequency. when the ISL95813 is in continuous conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3 ? modulator. section ?r3? modulator? on page 9 explains that the effective sw itching frequency will increase during load insertion and will de crease during load release to achieve fast response. on the other hand, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. change s. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. program 1 pin prgm1 programs i ccmax register and switching frequency. for proper operation, it is recommended the 1% resistor value called out in the table be used in the final application. program 2 pin prgm2 pin programs the both boot up voltage v boot , and the vid slew rate. for proper operation, it is recommended the 1% resistor value called out in the table be used in the final application. v droop r droop i droop = (eq. 3) vcc sense v + droop v dac vss sense + = (eq. 4) vcc sense vss sense ? v dac r droop i droop ? = (eq. 5) table 2. program 1 resistor values r_prog1 (3 % , k ? ) i ccmax (a) f sw (khz) 1.0 17 425 5.76 21 9.31 28 13.3 33 17.4 35 21 40 24.9 17 550 28.7 21 33 28 42.2 33 49.9 35 57.6 40 64.9 17 700 eco 73.2 21 80.6 28 90.9 33 102 35 113 40 124 17 700 pro 137 21 154 28 169 33 187 35 205 40 table 3. program 2 resistor values r_prog2 (3%, k ? )v boot (v) vid slew (mv/s) 1.0 0 12 5.76 1.65 9.31 1.7 13.3 1.75 http://www..net/ datasheet pdf - http://www..net/
ISL95813 14 fn8449.0 may 15, 2013 power state modes table 4 shows the power state operation mode. for ps0 and ps1, the ISL95813 operates in ccm while in ps2 and ps3 the device enters dcm. in ps4, ISL95813 enters a very low power state and shuts down all the drivers and internal circui ts. in this mode the controller only accepts setvid-fast and se tvid-slow commands, all other svid commands will be rejected. ISL95813 quiescent power is about 0.5mw in ps4. dynamic operation the ISL95813 responds to vid changes by slewing to the new voltage at a slew rate indicated in the setvid command. there are three setvid slew rates, namely setvid_fast, setvid_slow and setvid_decay. setvid_fast command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 12mv/s slew rate or the fast slew rate set by r_prog2. setvid_slow command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 3mv/s slew rate. setvid_decay command prompts the controller to enter de mode. the output voltage, v core , will decay down to the new vid value at a slew rate determined by the load as shown in equation 6. overvoltage protection is blanked during vid down transition in de mode until the output voltage is within 60mv of the vid value. if the voltage decay rate is too fast, the controller will limit the voltage slew rate at setvid_slow slew rate. alert# will be asserted low at the end of setvid_fast and setvid_slow vid transitions. figure 17 shows setvid decay pre-emptive behavior. the controller receives a setvid_d ecay command at t1. the vr enters de mode and the output voltage vo decays down slowly. at t2, before vo reaches the intended vid target of the setvid_decay command, the controller receives a setvid_fast (or setvid_slow) command to go to a voltage higher th an the actual vo. the controller will react immediately and slew vo to the new target voltage at the slew rate specified by the setvid command. at t3, vo reaches the new target voltage and the controller asserts the alert# signal. the r 3? modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. current monitor the controller provides the current monitor function. imon pin reports the inductor current. the imon pin outputs a high-speed analog current source that is 1/4 of the droop current flowing out of the fb pin. thus becoming equation 7: as the typical applications diagra m shows in figure 1, a resistor r imon is connected to the imon pin to convert the imon pin 17.4 1.75 24 21 1.7 24.9 1.65 28.7 0 33 0 40 42.2 1.65 49.9 1.7 57.6 1.75 64.9 1.75 45 73.2 1.7 80.6 1.65 90.9 0 102 0 53 113 1.65 124 1.7 137 1.75 154 1.75 80 169 1.7 187 1.65 205 0 table 4. power state operation mode power state configuration ps0 1-phase ccm ps1 1-phase ccm ps2 1-phase de ps3 1-phase de ps4 very low power state table 3. program 2 resistor values (continued) r_prog2 (3%, k ? )v boot (v) vid slew (mv/s) dv core dt ------------------ - i out c out ------------ = (eq. 6) figure 17. setvid decay pre-emptive behavior vo setvid_decay setvid_fast/slow t_alert vid alert# t1 t2 t3 i imon 0.25 i droop = (eq. 7) http://www..net/ datasheet pdf - http://www..net/
ISL95813 15 fn8449.0 may 15, 2013 current to voltage. a capacitor should be paralleled with r imon to filter the voltage information. th is voltage is sampled with an internal adc to produce a digital imon signal that can be read through the serial communications bus. the imon pin voltage range is 0v to 1.2v. the controller monitors the imon pin voltage and consid ers that ISL95813 has reached i ccmax when imon pin voltage is 1.2v. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, the phase node sits at a negative voltage equal to the mosfet r dson voltage drop. a phase comparator inside the controller monitors the phase volt age during the on-time of the low-side mosfet and compares it against a threshold to determine the zero-crossing point of the inductor current. should the inductor current not reach zero when the lower fet turns off, it will then flow through the low-side mosfet body diode, decreasing the voltage on the phase node until the inductor current completely decays to zero. when the inductor current finally reaches 0a phase is considered to be in tri-state mode and its voltage floats to the set v out value. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, current will then flow through the high-side mosfet body diode, causing a voltage spike on phase which will decay to the set v out voltage as phase tri-states. the controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low- side mosfet body diode conducts for approximately 30ns to minimize the body diode-related loss. protection the ISL95813 provides the designer with overcurrent, overvoltage, and over-temperature protection. the controller determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold as table 5 shows. it declares ocp when i droop is above the threshold for 120s. for over temperature and overcurrent faults, the controller takes the same actions: de-assertion of pgood and turn-off of all the high-side and low-side power mo sfets. any residual inductor current will decay through the mosfet body diodes or load. the controller will declare an over voltage fault and de-assert pgood if the output voltage exceeds the vid set value by +300mv. the controller will immediately declare an ov fault, toggle pgood to ground. the low-side power mosfet remains on until the output voltage is pulled down below the vid set value before being shut off, and placing phase into tri-st ate. if the output voltage rises above the vid set value +300mv again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. all the above fault conditions can be reset by toggling vr_on low. when vr_on is brought back to its high operating levels a soft-start will occur. table 5 summarizes the fault protections. supported data and configuration registers the controller supports the fo llowing data and configuration registers. table 5. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vdd toggle overvoltage +300mv immediately pgood latched low. actively pulls the output voltage to below vid value, then tri-state. table 6. supported data and configuration registers index register name description default value 00h vendor id uniquely identifies the vr vendor. assigned by intel. 12h 01h product id uniquely identifies the vr product. intersil assigns this number. 0ch 02h product revision uniquely identifies the revision of the vr control ic. intersil assigns this data. 04h 05h protocol id identifies what revision of svid protocol the controller supports. 03h 06h capability identifies the svid vr capabilities and which of the optional telemetry registers are supported. 81h 10h status_1 data register read after alert# signal. indicating if a vr rail has settled, has reached vr_hot# condition or has reached i ccmax . 00h 11h status_2 data register showing status_2 communication. 00h 12h temperature zone data register showing temperature zones that have been entered. 00h 1ch status_2_ lastread this register contains a copy of the status_2 data that was last read with the getreg (status_2) command. 00h 21h i ccmax data register containing the i ccmax the platform supports, set at start-up by resistors r_prog1. the platform design engineer programs this value during the design process. binary format in amps, i.e., 100a = 64h set by r_prog1 24h sr-fast slew rate normal. the fastest slew rate the platform vr can sustain. binary format in mv/s. i.e., 0ch = 12mv/s. set by r_prog2 http://www..net/ datasheet pdf - http://www..net/
ISL95813 16 fn8449.0 may 15, 2013 key component selection inductor dcr current-sensing network figure 18 shows the inductor dcr current-sensing network for a single phase solution. this loop monitors the voltage drop across the dcr creating by current flowin g in the inductor and feeds that information to the ISL95813 for i mon and load line purposes. the summed inductor current information is presented to the capacitor c n . equations 8 thru 12 describe the frequency-domain relationship between inductor total current i o (s) and c n voltagev cn (s): in the dcr network, transfer function a c (s) has unity gain at dc. as winding temperature increases, th e dcr of the inductor increases which causes a higher reading of the dc current flowing through the inductor. to compensate for this effect, the resistance of the ntc r ntc decreases as its temperature increases. choosing the remaining components of the dcr network correctly ensures that the capacitor voltage v cn accurately represents the total dc current through the inductor over the en tire operating temperature range. it is recommended when designing the dcr network to maintain v cn as the highest feasible fraction of the voltage that is dropped 25h sr-slow default is 4x slower than normal. binary format in mv/us. i.e., 03h = 3mv/s. can be configured by register 2ah. set by r_prog2 and register 2ah 26h v boot if programmed by the platform, the vr supports v boot voltage during start-up ramp. the vr will ramp to v boot and hold at v boot until it receives a new setvid command to move to a different voltage. set by r_prog2 2ah slow slew rate selector 01h = 1/2 of fast slew rate 02h = 1/4 of fast slew rate 04h = 1/8 of fast slew rate 08h = 1/16 of fast slew rate 02h 2bh ps4 exit latency report 48s 76h 2ch ps3 exit latency 38h 2dh enable to vr_ready latency c2h 30h v out max this register is programmed by the master and sets the maximum vid the vr will support. if a higher vid code is received, the vr will respond with ?not supported? acknowledge. b5h 31h vid setting data register containing currently programmed vid voltage. vid data format. 00h 32h power state register containing the current programmed power state. 00h 33h voltage offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is a sign bit, 0 = positive margin, 1 = negative margin. remaining 7 bits are # vid steps for the margin. 00h = no margin, 01h = +1 vid step 02h = +2 vid steps... 00h 34h multi vr config data register that configures multiple vrs behavior on the same svid bus. 00h 35h setregadr serial data bus communication address 00h table 6. supported data and configuration registers (continued) index register name description default value figure 18. dcr current-sensing network cn rntcs rntc rp io dcr l phase ri vcn rsum isumn isump v cn s () r ntcnet r ntcnet r sum + ------------------------------------------ dcr ?? ?? ?? i o s () a cs s () = (eq. 8) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- = (eq. 9) a cs s () 1 s l ------ - + 1 s sns ------------ - + ---------------------- - = (eq. 10) l dcr l ------------- = (eq. 11) sns 1 r ntcnet r sum r ntcnet r sum + ------------------------------------------ c n -------------------------------------------------------- = (eq. 12) http://www..net/ datasheet pdf - http://www..net/
ISL95813 17 fn8449.0 may 15, 2013 across the inductor?s dcr in order to ensure the droop circuitry on chip has a high signal level to operate with. while final component values should be fine tuned for a given application, a good starting point for the dcr temperature compensation network is as follows: rsum = 3.65k ? , rp = 11k ? , rntcs = 2.61k ? , and rntc = 10k ? (ert-j1vr103j). to check the operation of the compensation network apply the full load dc current and record the output vo ltage both immediately and once the circuit has reached its thermal equilibrium. a well designed ntc network can limit the amount of drift on the output voltage to within 2 mv. in order to achieve proper transient response it is also crucial that v cn (s) represents real-time i o (s) of the controller. this is done by matching the pole and zero present in a cs (s) to one another which sets the transfer function to unity gain for all frequencies. to ensure unity gain force l equal to sns and solve for c n as seen in equation 13. for example, with r sum = 3.65k ? , r p = 11k ? , r ntcs = 2.61k ? , r ntc = 10k ? , dcr = 1m ? , and l = 0.2h, equation 13 gives c n = 0.088f. with proper compensator design, figure 19 shows the expected load transient response waveforms. when the load current i o has a square change, the output voltage v o also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and the transient resp onse of the controller will degrade. when c n is too small, v o will sag excessively as seen in figure 20 and potentially trigger a system failure. figure 21 shows the transient response when c n is sized too large. in this case v o will reach its expected droop voltage much too slowly with respect to the load insertion. should a load release occur during this time there will be excessive overshoot on v o which may potentially hurt cpu reliability. figure 22 gives an example of ri ng back on the output voltage during load transient response. ri ng back occurs when the load current i o has a fast step change, but the inductor current i l cannot accurately track it. instead, i l responds in a first order fashion due to the nature of current loop. instead of the output accurately responding to the load insertion the parasitic esr and esl properties of the output capacitors cause an abrupt dip in the voltage. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , introducing the ring back into the response. this phenomenon can be mitigated through the use of very low esr and esl ceramic capacitors for the output filter. figure 23 shows two circuits for ring back reduction that can be used in conjunction with low parasi tic output filter components if need be. normally c n , the capacitor used to match the inductor time constant, is implemented through the parallel combination of two or more capacitors shown in figure 23 as c n.1 and c n.2 . the first option to reduce ring back is to add resistor r n in series to c n.1 . at steady state operation c n.1 + c n.2 provide the desired c n capacitance calculated from eq uation 11. at the beginning of i o change however, the effective capacitance of the matching c n l r ntcnet r sum r ntcnet r sum + ------------------------------------------ dcr -------------------------------------------------------------- - = (eq. 13) figure 19. desired load tr ansient response waveforms o i v o figure 20. load transient response when c n is too small o i v o figure 21. load transient response when c n is too large o i v o figure 22. output voltage ring back problem o i v o l i ring back http://www..net/ datasheet pdf - http://www..net/
ISL95813 18 fn8449.0 may 15, 2013 network is less because r n increases the impedance of the c n.1 branch. as figure 20 explains, v o tends to dip when c n is too small which will reduce the amount of ring back seen during load transients. this effect is more pronounced when c n.1 is larger than c n.2 as well as when the value of r n is increased. however, when designing the final circuit, care should be taken not to make r n larger than necessary or make c n.1 much larger than c n.2 or else excessive ripple will be seen on v cn . it is recommended to keep c n.2 greater than 2200pf and r n in the range of only few ohms. the final values of c n.1 , c n.2 and r n should be determined through tuni ng the load transient response waveforms on an actual board to be used in the end application. the second method for ring back reduction is to add the series combination of r ip and c ip in parallel with r i . these components should be sized to provide a lower impedance path than r i alone at the beginning of an i o transient. during steady state operation r ip and c ip do not have any effect on the controller?s operation. through proper selection of r ip and c ip values, i droop can more closely resemble i o rather than i l , and ring back on the output voltage will not be seen. the recommended value for r ip is 100 . while the recommended range for c ip is 100pf to 2000pf though final values should be tuned to the final end product board. it should be noted that the r ip -c ip branch may distort the i droop signal by introducing sharp spikes to the normally triangular waveform which may adversely affect the average value detection and therefore may affect ocp accuracy. discretion is recommended when implementing this second ring back reduction method in order to maintain a robust system. resistor current-sensing network above is an example of using a re sistor sense method of sensing load current instead of scr sensing. in this method, the inductor current creates a voltage across r sen which is then filters and averaged by the rc filter composed of r sum and c n . the results voltage, v cn , is then fed into the current sense amplifier on chip through the isump and isumn pins. no ntc network is needed in this scenario because the value of the current sensing resistor, r sen , will not vary appreciably over temperature. the design equations for this method of current sensing are given in equations 14 through 16. recommended values for r sum and c n are 1k ? and 5600pf respectively. as with the dcr me thod, final values should be tuned in on the actual application board. overcurrent protection refer to equation 2 on page 12 and figures 18, 22 and 25; resistor r i sets the droop current i droop . table 5 shows the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, assume the ocp threshold is 60a for 1-phase solution. we will design i droop to be 48a at full load. from equation 8 in inductor dcr sensing applications assuming dc conditions gives the relationship of v cn (s) to i o (s) in equation 17. figure 23. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isump isumn rip cip optional vcn cn.1 rn optional figure 24. resistor current-sensing network cn io dcr l phase vcn rsen ri rsum isumn isump v cn s () r sen i o s () a rsen s () = (eq. 14) a rsen s () 1 1 s rsen ----------------- + --------------------------- = (eq. 15) rsen 1 r sum c n ---------------------------- - = (eq. 16) v cn r ntcnet r ntcnet r sum + ------------------------------------------ dcr i o = (eq. 17) http://www..net/ datasheet pdf - http://www..net/
ISL95813 19 fn8449.0 may 15, 2013 substituting of equation 17 into equation 2 yields equation 18 which can then be solved for r i . expanding the r ntcnet term using equation 9 and applying of the ocp condition in equation 19 gives the final expression for r i in equation 20. where i omax is the full load current, i droopmax is the corresponding droop current. for example, given r sum = 3.65k , r p = 11k , r ntcs = 2.61k , r ntc = 10k , dcr = 0.9m , i omax =33a and i droopmax = 48a, equation 20 gives r i =381 . when resistor sensing meth ods are used, assuming dc conditions in equation 14 gives the following relationship between v cn and i o . substituting equation 21 into equation 2 gives equation 22: therefore assuming the ocp conditions put in place previously in equation 23 gives equation 24: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given r sen = 1m , i omax = 33a and i droopmax = 48a, equation 24 gives r i =687 . as before, with the dcr and r sense components, the final value of ri should be tuned to fit the final application. load line slope for this section please refer to figure 16 on page 12. in order to calculate the load line in dcr sense applications start by substituting equation 8 into equation 2 to give a more detailed expression for i droop . next, substitute the new expression for i droop into equation 3 and solve for the dc load line, shown in equation 25: for resistor sensing, substitute equation 22 into equation 3 to get the load line slope expression : to find the value of r droop , substitute equation 19 into equation 25 and solve for r droop , or substitute equation 23 into equation 26 and solve for r droop . both methods give the same result, which is shown in equation 27: one can use the full load condition to calculate r droop . for example, given i omax = 33a, i droopmax = 48a and ll = 2.0m , equation 27 gives r droop = 1.37k . it is recommended to start with the r droop value calculated by equation 27 and fine tune it on the actual board to get accurate load line slope. one should record the output voltage readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. compensator figure 19 shows the desired load transient response waveforms while figure 25 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e. constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. a voltage regulator with an active droop function is a dual-loop system consisting of a voltage loop and a current based droop loop, of which neither is sufficient to describe the entire system alone. figure 26 conceptually shows t1(s) measurement set-up and figure 27 conceptually shows t2 (s) measurement set-up. the vr senses the inductor current, multiplie s it by a gain of the load line slope, then adds it on top of the sensed output volt age and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the vo ltage loop before the summing node. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain i droop 1 r i ----- r ntcnet r ntcnet r sum + ------------------------------------------ dcr i o = (eq. 18) r i r ntcnet dcr i o r ntcnet r sum + () i droop ---------------------------------------------------------------------- = (eq. 19) r i r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- dcr i omax r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- r sum + ?? ?? ?? i droopmax ------------------------------------------------------------------------------------------------------------------ = (eq. 20) v cn r sen i o = (eq. 21) i droop 1 r i ----- r sen i o = (eq. 22) r i r sen i o i droop ------------------------ = (eq. 23) r i r sen i omax i droopmax ----------------------------------- - = (eq. 24) ll v droop i o ------------------ - r droop r i ------------------- r ntcnet r ntcnet r sum + ------------------------------------------ dcr == (eq. 25) ll v droop i o ------------------ - r sen r droop r i --------------------------------------- == (eq. 26) r droop i o i droop ---------------- ll = (eq. 27) figure 25. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr http://www..net/ datasheet pdf - http://www..net/
ISL95813 20 fn8449.0 may 15, 2013 with closed droop loop. it has more meaning of output voltage response. only t2(s) can be actu ally measured in a laboratory setting on the ISL95813 regulator. typically, one should design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. current monitor refer to equation 7 on page 14 for the imon pin current expression. looking at the ?typical 40amax, 12.6, application diagram? on page 1, the current flowing fr om the imon pin goes through r imon creating a voltage v rimon . the expression for voltage is expressed in equation 28: to expand this expression, first solve equation 27 for i droop giving equation 29: next, substitute equation 29 into equation 28 giving the final expression for v rimon . assuming i o = i omax and rewriting equation 30 gives equation 31 for choosing the value of r imon . for example, given ll = 2.0m , r droop = 1.37k , v rimon =1.2v at i omax =33a, equation 31 gives r imon =100k . the results from equation 29 should be treated as a starting point for the design and the resistor value shou ld be finalized on an actual application board. a capacitor c imon should be but in parallel with r imon to filter the imon pin voltage. it is recommended to have a time constant long enough to remove any switching frequency ripples from the imon signal. slew rate compensation circuit for vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate while maintaining an output voltage, v core, slew rate of 10mv/s. figure 26. loop gain t1(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer figure 27. loop gain t2(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer v rimon 0.25 i droop r imon = (eq. 28) i droop i o r droop ------------------- ll = (eq. 29) v rimon 0.25i o ll r droop ----------------------------- - r imon = (eq. 30) r imon v rimon r droop 0.25i o ll ---------------------------------------------- = (eq. 31) figure 28. slew rate compensation circuit for vid transition x 1 e/a dac vid rdroop idroop_vid vdac fb comp vcore vss sense vids rtn vss internal to ic rvid cvid vid vfb vcore ivid idroop_vid ivid optional http://www..net/ datasheet pdf - http://www..net/
ISL95813 21 fn8449.0 may 15, 2013 figure 28 shows the waveforms of vid transition. during vid transition, the output capacitor is being charged and discharged, causing c out x dv core /dt current on the inductor. the controller senses the inductor current increase during the up transition (as the i droop_vid waveform shows) and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to get the correct v core slew rate during vid transition, one can add the r vid to c vid branch, whose current i vid cancels i droop_vid . it?s recommended to choose the r vid and c vid values from the reference design as a starting point. then tweak the actual values on the board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual grou nd in small signal sense. the r vid to c vid network is between the virtual ground and the real ground, and hence has no effect on transient response. vr_hot#/alert# behavior the ISL95813 sources 60a of current out of the ntc pin at 1khz with a 50% duty cycle. the current source flows through the respective ntc resistor network on the pin and creates a voltage that is monitored by the controller through an a/d converter (adc) to generate the t zone value. table 7 shows the programming table for t zone . the user needs to scale the ntc resistor network such that it ge nerates the ntc pin voltage that corresponds to the left-most column. do not use any capacitor to filter the voltage. figure 29 shows how the ntc and the ntcg network should be designed to get correct vr_hot#/alert# behavior when the system temperature rise s and falls which is manifested as the ntc pin voltage rising and falling. the series of events are: 1. the temperature rises so the ntc pin voltage drops. t zone value changes accordingly. 2. the temperature crosses the threshold where t zone register bit 6 changes from 0 to 1. 3. the controller changes status_1 register bit 1 from 0 to 1. 4. the controller asserts alert#. 5. the cpu reads status_1 register value to know that the alert assertion is due to t zone register bit 6 flipping. 6. the controller clears alert#. 7. the temperature continues rising. 8. the temperature crosses the threshold where t zone register bit 7 changes from 0 to 1. 9. the controllers asserts vr_hot# signal. the cpu throttles back and the system temperature starts dropping eventually. 10. the temperature crosses the threshold where t zone register bit 6 changes from 1 to 0. this threshold is 1 adc step lower than the one when vr_hot# gets asserted, to provide 3% hysteresis. 11. the controllers de-asserts vr_hot# signal. 12. the temperature crosses the threshold where t zone register bit 5 changes from 1 to 0. this threshold is 1 adc step lower than the one when alert# gets asserted during the temperature rise to provide 3% hysteresis. 13. the controller changes status_1 register bit 1 from 1 to 0. 14. the controller asserts alert#. 15. the cpu reads status_1 register value to know that the alert assertion is due to t zone register bit 5 flipping. 16. the controller clears alert#. table 7. t zone values vntc (v) tmax (%) t zone 0.84 >100 ffh 0.88 100 ffh 0.92 97 7fh 0.96 94 3fh 1.00 91 1fh 1.04 88 0fh 1.08 85 07h 1.12 82 03h 1.16 79 01h 1.2 76 01h >1.2 <76 00h 1 bit 6 =1 bit 7 =1 bit 5 =1 temp zone register 0001 1111 0011 1111 0 1 11 1111 1 111 1111 0 1 11 1111 0011 1111 0001 1111 status 1 register = ?001? = ?0 1 1? = ?0 0 1? temp zone 7 2 3 5 svid alert# vr_hot# 4 gerreg status1 8 6 9 10 11 1111 1111 0111 1111 0011 1111 0001 1111 12 13 15 gerreg status1 14 16 3% hysteresis vr temperature figure 29. vr_hot#/alert# behavior http://www..net/ datasheet pdf - http://www..net/
ISL95813 22 fn8449.0 may 15, 2013 layout guidelines ISL95813 symbol layout guidelines bottom pad gnd connect this ground pad to the ground plane through low impedance path. recommend use of at least 5 vias to connect to ground planes in pcb internal layers. 18, 19, 20 sclk, sda, alert# follow intel recommendation. 1 vr_on no special consideration. 2 pgood no special consideration. 3 imon no special consideration. 4 vr_hot# no special consideration. 5 ntc the ntc thermistor needs to be placed close to the ther mal source that is monitored to determine cpu vcore thermal throttling. recommend placing it at the hottest spot of the cpu vcore vr. 6 comp place the compensator components in general proximity of the controller. 7fb 10 isumn place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to the inductor so it senses the inductor temperature correctly. the power stage requires a pair of vsump and vsumn signals to the controller. these two si gnal traces should run in a parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. if possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the cent er of the pads. if no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. the following drawings show the two preferred ways of routing current sensing traces. 9isump 13 boot1 use decent wide trace (>30mil). avoid any sensitive analog signal trace from cros sing over or getting close. 14 ug run these two traces in parallel fashion with a decent width (>30mil). avoid any sensit ive analog signal trace from crossing over or getting close. recommend routing phase tr ace to high-side mosfet source pins instead of general copper. 15 phase 16 lg use a decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. 12 vcc a capacitor decouples it to gnd. plac e it in close proximity of the controller. 17 prog1 connect a resistor to gnd. place it in close proximity of the controller. 11 prog2 connect a resistor to gnd. place it in close proximity of the controller. 8 rtn place the rtn filter in close proximit y of the controller for good decoupling. inductor current-sensing traces vias inductor current-sensing traces http://www..net/ datasheet pdf - http://www..net/
ISL95813 23 fn8449.0 may 15, 2013 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6 http://www..net/ datasheet pdf - http://www..net/
ISL95813 24 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8449.0 may 15, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change may 15, 2013 fn8449.0 initial release http://www..net/ datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of ISL95813

	To Download ISL95813 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .